CMS Upgrade

The upgrade program of the CMS detector is being designed to accomodate to the LHC plans for increasing its luminosity from its nominal design value of 1034 cm-2 s-1 to up to a factor 10, which implies the redesign and replacement of certain parts of the detector. A first upgrade program, so called Phase 1 in CMS, was built to cope with up to a factor 2 increase of instantaneous luminosity by 2016 and a Phase 2 upgrade program that should cope with up to a factor 10 integrated luminosity (3000 fb-1) and factors 5 to 10 instantaneous luminosity by 2023.

The CIEMAT group has been involved in the upgrade activities of the CMS DT project since the very beggining. We have had important responsibilites during the Phase 1 Upgrade (DT Upgrade coordinator) and have lead the upgrade program from its conception until now, when it is close to finalization.

The DT Phase 1 upgrade program consisted in the Sector Collector relocation during 2013-2014 with the extraction of the second level of electronics from the cavern into the counting room, and the corresponding copper to optical converters. This task was followed by the installation of new second level of trigger (TwinMux) and readout electronics (uROS) as part of the Phase 1 Upgrade.

The mid term future of LHC includes a major upgrade around 2020 which will increase its integrated luminosity (rate of collisions) by a factor of 10 beyond the original design value. This will require a redesign and replacement of certain parts of the detector. In particular in the DT chambers a significant portion of the readout and trigger electronics will be substituted. Our group is currently involved in the R&D of these detector upgrade activities. 

More information about the electronics designed by our group can be found in the CIEMAT DT electronics web page



  • TwinMux and uROS. CMS Phase 1 Upgrade
  • HL-LHC CMS DT Upgrade (Phase 2)
  • DT Sector Collector Relocation

Once the Sector Collector relocation phase was achieved, we proceeded with the replacement of the second level of trigger and readout electronics by a higher performant system.

The trigger electronics, TSC, had to be upgraded as part of the Level 1 Trigger upgrade project in order to allow improved performance that satisfies the optimal physics in a higher luminosity regime. On the other hand, the ROS-25 board needed to be replaced in order to increase the processing speed to cope with the increased occupancy due to the higher luminosity (up to a factor 2 the LHC nominal design).

A single design was foreseen for both types of boards since the main difference is the input data format and speed (480 Mbps for the trigger and 240 Mbps for the readout), which could be easily accomodated. The board is built around a Virtex 7 FPGA and contains up to 72 input optical links and 10 Gbps outputs. It follows the uTCA telecommunications standard. It is called TwinMux board for the trigger case and uROS for the readout case, with different firmware implemented in the FPGA.


Image of the TwinMux/uROS board.

Image of the uROS slice test at P5 operating under collisions.